As the application range of chips widens continuously, a chip needs to communicate with an external Host in real time so as to receive an instruction from the Host to perform a corresponding action, which requires the chip to be provided with an IO interface circuit to transmit the instruction of the external Host to the inside of the chip or feedback the execution result of the chip back to the external Host. Thus, the IO interface circuit should address problems existing in signal level shift and signal driving. Existing IO interface circuits perform a level shift by introducing the interface level of the external Host of a chip to the inside of the chip for a level shift with an internal power supply of the chip or by generating an external interface power supply inside the IO interface circuits using a Low Dropout Regulator (LDO).
In a case where the interface level of the Host of a chip is introduced to the inside of the chip for a level shift with an internal power supply of the chip, a specific pin for introducing an IO interface level is needed, which will absolutely result in addition of a pin on a chip and consequentially increase the cost of the chip in processes such as banding, encapsulation and so on and degrade the competitiveness of the chip; and in a case where a level shift is realized by generating an external interface power supply through an internal LDO, it is needed to generate the reference voltage and the reference current of the LDO at the same time, which makes it more difficult to realize a chip, increases the standby power consumption of the chip and narrows the application range of the chip.